Implementation of a programmable neuron in CNTFET technology for low-power neural networks

Document Type : Reasearch Paper

Author

Department of Electronics, Urmia University of Technology, Urmia, West Azerbaijan, Iran.

Abstract

Circuit-level implementation of a novel neuron has been discussed in this article. A low-power Activation Function (AF) circuit is introduced in this paper, which is then combined with a highly linear synapse circuit to form the neuron architecture. Designed in Carbon Nanotube Field-Effect Transistor (CNTFET) technology, the proposed structure consumes low power, which makes it suitable for the implementation of high-throughput Neural Networks (NNs). The main advantage of the proposed AF circuit is its higher accuracy for the generation of hyperbolic tangent function compared to the previously reported works. Moreover, the programmability feature for the slope and the position shifting enhances the adaptability of the designed neuron for different types of neural systems, especially Multi-Layer Perceptrons (MLPs). There is also excellent compatibility between the synapse and activation circuits, which illustrates another notable privilege of the proposed neuron. Simulations using HSPICE for CNTFET 32 nm standard process have been carried out for the designed scheme to indicate the correct operation. Based on the results, all of the claimed advantages can be proved clearly while the power dissipation is 6.11µW from the 0.9V power supply. Also, an accuracy of 98% has been achieved for the AF circuit.

Keywords


[1]           Hentrich M., (2015), Methodology and Coronary Artery Disease Cure, SSRN.
[2]           Zurada J., (1992), Introduction to Artificial Neural Systems, West Publishing Company, USA.
[3]           McCulloch W. S., Pitts W., (1943), A logical calculus of the ideas immanent in nervous activity. The bull. Math. Biophys. 5: 115–133.
[4]           Ota Y., Wilamowski B. M., (1994), VLSI Implementation of a Programmable Current-Mode Neural Network, Proceedings: Intellig. Eng. Sys. Through Artific. Neural Networks, ANNIE'94 Conf., St. Louis, 4: 71-76.
[5]           Cauwenberghs G., Bayoumi M., (1999), Learning on Silicon., Adaptive VLSI Neural Systems, Kluwer Academic Publishers.
[6]           Wojtyna R., Talaska T., (2006), Transresistance CMOS neuron for adaptive neural networks implemented in hardware, Bull. Pol. Acad. Sci. 54: 443-448.
[7]           Hosseinzadeh Namin A., Leboeuf K., Muscedere R., Wu H., Ahmadi M., (2009), Efficient hardware implementation of the hyperbolic tangent sigmoid function, IEEE Int. Symp. Circ. Sys. 2117-2120.
[8]                         Azizian S., Fathi K., Mashoufi B., Derogarian F., (2011), Implementation of a programmable neuron in 0.35μm CMOS process for multi-layer ANN applications. Eurocon-Int. Conf. Comp. Tool. 1-4.
[9]           Khodabandehloo G., Mirhassani M., Ahmadi M., (2012), Analog implementation of a novel resistive-type sigmoidal neuron. IEEE-Transact.  Very Large Scale Integ. (VLSI) Systems 20: 750-754.
[10]        Shamsi J., Amirsoleimani A., Mirzakuchaki S., Ahmade A., Alirezaee Sh., Ahmadi M., (2015), Hyperbolic tangent passive resistive-type neuron. 2015 IEEE- Int. Symp. Circ. Sys. (ISCAS). 581-584.
[11]        Azizian S., Aziz Aghchegala V., Azizian S., Sefidgar Dilmaghani M., (2019), CMOS bulk-controlled fully programmable neuron for artificial neural networks. IETE J. Res. 65: 320-328.
[12]                      Liu C., Cheng H., (2013), Carbon nanotubes: Controlled growth and application. Mater. Today. 16: 19-28.
[13]        Avouris P., Afzali A., Appenzeller J., Chen J., Freitag M., Klinke C., Lin Y.-M., Tsang J. C., (2004), Carbon nanotube electronics and optoelectronics. Tech. Digest-IEEE Int. Elec. Dev. Meeting (IEDM). 525-529.
[14]        Franklin A. D., (2013), Electronics: The road to carbon nanotube transistors. Nature. 498: 443–444.
[15]        Rahnamaei A., Zare Fatin G., Eskandarian A., (2019), Design of a low power high speed 4-2 compressor using CNTFET 32 nm technology for parallel multipliers. Int. J. Nano Dimens. 10: 114-124.
[16]        Rahnamaei A., Zare Fatin G., Eskandarian A., (2019), High speed Radix-4 Booth scheme in CNTFET technology for high performance parallel multipliers. Int. J. Nano Dimens. 10: 281-290.
[17]        Yousefi R., Saghafi K., Moravvej-Farshi M. K., (2010), Application of neural space mapping for modeling ballistic carbon nanotube transistors. Iranian J. Elec. Elec. Eng. 6: 70-76.
[18]        Abdollahzadeh Badelbo R., Farokhi F., Kashaniniya A., (2013), Efficient parameters selection for CNTFET modelling using Artificial Neural networks. Int. J. Smart Elec. Eng. 2: 217-222.
[19]        Zhang J., Chang Sh., Wang H., He J., Huang O., (2014), Artificial Neural network based CNTFETs modeling. Appl. Mech. Mater. 667: 390-395.
[20]        Friesz A. K., Parker A. C., Zhou Ch., Philip Wong H.-S., Deng J., (2007), A Biomimetic carbon nanotube synapse circuit. Biomed. Eng. Soc. (BMES) Annual Fall Meeting.
[21]        Joshi J., Zhang J., Wang Ch., Hsu Ch.-Ch., Parker A. C., Zhou Ch., Ravishankar U., (2011), A biomimetic fabricated carbon nanotube synapse for prosthetic applications. IEEE/NIH Life Sci. Sys. Appl. Workshop (LiSSA).
[22]        Najari M., El-Grour T., Jelliti S., Mousa Hakami O., (2016), Simulation of a spiking neuron circuit using carbon nanotube transistors. Proceed. Fifth Saudi Int.Meeting on Front. Phys. (SIMFP2016).
[23]        Fathi A., Azizian S., Sharifan N., (2017), Sensors and amplifiers: Sensor output signal amplification systems, In Handbook of Research on Nanoelectronic Sensor Modeling and Applications, 423-504, IGI Global.