Document Type : Reasearch Paper
Authors
1 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India
2 Department of Electronics and Communication Engineering, Narula Institute of Technology, Kolkata, India
3 Academic Advisor, Kingstone Educational Institute, Kolkata, India
Abstract
Keywords
Main Subjects
INTRODUCTION
The limitations of conventional Complementary Metal Oxide Semiconductor (CMOS) based VLSI technology [1] lead the researchers’ bias towards nanotechnology paradigm which has been revolutionized by the application of Quantum-dot Cellular Automata (QCA) [2] since last two years. In QCA, binary logic computation is possible without the application of traditional voltage and current flow. A Quantum Cell, the basic structure of QCA technology, contains four tiny semiconductor dots with two excess electrons. The positions of the excess electrons within the squared QCA cell define the logic state as either 1 or 0. The Columbic interactions among the array of QCA cells keep the information flowing within the circuit.
The extreme high packing density, ultra-high speed operation and extreme low power dissipation are the phenomenal features of this nanotechnology [3]. There are four basic types of QCA namely, Metal-dot QCA, Semiconductor QCA, Molecular QCA and Magnetic QCA [4-7]. The gallium arsenide based heterostructure semiconductor QCA technology and its related design parameters have been used in this work owing to the significant advancement in semiconductor fabrication technology in subnanometre regime [8-9].
After the experimental fabrication of coplanar silicon dangling bond based quantum-dots [10], researchers are now working on the multilayer structures of QCA [11].
However, some issues of concern with this technology still remain such as fabrication faults at the layout stage and input-output fixation with real time physical parameters [12].
The error detection and correction codes are the contingent portion in binary data transmission networks [13]. The transmitted logic 0’s and 1’s may change their logic at the receiver end due to the presence of noise in the environment. The parity generators are inherent part for error detection and correction in the transceiver system [14-20].
The main aim of this work is focused on the generic design of even and odd parity generators by using the LTEx methodology [21-22] of QCA. In this methodology, the two-input LTEx module conforms to the Exclusive-OR output. Exclusive OR Gate is the key module of the parity generators, which are constructed using the two-input LTEx modules. After the successful instantiation of lower order parity generators, higher order parity generators are also proposed to be used in multi-level nano-communication circuits. The Costα analysis [22-23] of the proposed LTEx parity generator circuits is carried out with the best reported ones available in the literature to analyze the complexity and irreversible power dissipation that establishes the superiority of the proposed generator over the others.
This paper is organized as follows: Section 2 discusses the background of QCA. It shows the basic structures of QCA and retrospect’s the QCA design metrics. Literature surveys are also presented here for the key parity generators available as of now. Section 3 introduces the layouts of parity generators by using Layered T Gate. A generic methodology to formulate the n-bit parity generator layouts for high fan-in multi-level QCA nano-communication circuits is proposed in this section. The comparison of parity generator designs of different bit length with the existing designs in terms of QCA design metrics are presented in Section 4. Finally, Section 5 concludes with the results.
COMPUTATIONAL METHODS
Basic structure of QCA circuits
The quantum cell comprises of four quantum dots placed at the corners of a square. Free electrons are located on two of those four diagonal dots. A single quantum cell is considered to form the computational elements with their interconnecting wires of a circuit as shown in Fig. 1(a), Quantum Cell, Polarization P. The orientation of electrons within the quantum cell corresponds to the binary representation of logic 1 or 0 as given in Fig. 1(b) P = +1 and 1(c) P = -1 respectively. An isolated quantum cell holds either of these two possible orientations which are called the ground states [5, 23]. Though a quantum cell is surrounded by the neighbor quantum cell, but tunneling is allowed only between the electrons. The electrons from the neighbor cells cannot tunnel as they fetch high inter-dot potential barrier.
The foremost logical structures formed by the electro-mechanically coupled quantum cells comprises of Binary Wire, conventional seven-cell inverter and the Majority Voter. The binary wire simply carries the information from one level to the next level of the QCA circuit. The Boolean inverter takes the input, inverts it and passes the same on to the output cell. The majority voter fetches the logic of the three inputs A, B and C. It decides the majority among these three logics and generates output Z in favour of the majority logic. Such computation of Majority Voter is validated by the equation Z = M (A, B, C) = AB + BC + CA. The structures of binary wire, conventional seven-cell inverter and Majority voter are shown in Figs. 2(a) Majority Voter, (b) Seven Cell Inverter and (c) Binary Wire respectively.
QCA clock
Every QCA circuit needs an external field, which is termed as QCA clock to control the flow of information [24]. This clock has four phases namely switch (phase 1), hold (phase 2), release (phase 3) and relax (phase 4) as mentioned in Fig. 3 QCA Clock Zone. The switch phase starts with unpolarized quantum cell and lower inter-dot potential barrier. Such barriers are increased and the quantum cell becomes polarized according to its previous cell’s logic. At the end of this phase, the barriers attain maximum value that suppresses further intra-dot electron tunneling. As a result, the logic of the quantum cell becomes fixed. In the hold state, the barriers remain at a high state so that the quantum cell retains its polarization. The release phase starts decreasing the barriers and the quantum cell begins to relax. Finally, the relax phase pushes the cell to an unpolarized state.
Qca logic gate
Based on QCA technology, several researches have been done in the following computational reduction techniques such as: And-Or-Invert (AOI) Gate, Nand-Nor-Invert (NNI) Gate, Universal QCA Logic (UQCALG) Gate, Coupled Majority Voter Minority (CMVMIN) Gate, FNZ Gate and Layered T Gate [21]. The biplanar-structure based Layered T Gate has been introduced to perform the universal NAND/NOR operation in QCA technology [22]. The rotated cell by using two-dimensional electron gases can implement the upper layer cells. The equation of Layered T Gate is given by equation (1):
Design metrics of QCA
The evaluation of QCA layout designs of digital circuits like adders, multiplexers, memories and other significant blocks of arithmetic logic unit is carried out in terms of the following points: (i) O-Cost, (ii) Effective area, (iii) Costα (iv) Irreversible Power Dissipation and (v) Complexity [23-24]. To obtain the most favourable QCA layout designs, the minimal value of above mentioned parameters are desirable. The definitions of these parameters are discussed below:
(i) O-Cost: The number of quantum cells in a specific QCA layout is termed as O-Cost [21-22, 25]. The QCA layout with lower value of O-Cost is the expected parameter to design an area-delay-power efficient circuit. For example, the two-input multiplexer of Fig. 4 has 67 quantum cells, making the value of the O-Cost to be 67 [26].
(ii) Effective Area: The total area of the QCA layout is called effective area. The rectangular box that covers 81648 nm2 in Fig. 4 two inputs Multiplexer in [26] is the effective area for the specified two-input multiplexer.
(iii) Costα: The QCA layout design metric that includes the performance, complexity, fabrication difficulty and irreversible power dissipation is called Costα [23]. The expression of the Costα is given by:
(2)
In equation (2), M=number of Majority Voter, I=number of Inverter and C=Crossover. The value of M, I, C, T for two-input multiplexer of Fig. 4 become 3, 2, 2, 1 respectively. Hence the calculation for Costα becomes (32+2+22)*1=15. The value of C becomes 1 for a coplanar QCA layout but the multilayer structure makes C=3, as minimum three layers are needed above the main cell layer to make the layout operable [21-22].
(iv) Irreversible Power Dissipation: According to its definition [22], the term (M + I + C) becomes the Irreversible Power Dissipation in Majority Logic Synthesis. But for Layered T logic reduction technique, the term (LT + I + C) counts Irreversible Power Dissipation.
(v) Complexity: The number of layer requirements in a QCA layout is complexity. As coplanar crossover is used in the layout of Fig. 3, the complexity C becomes 1.
Literature survey
Numerous research works have been published now; showcasing mostly the design of even parity generator structures such [14-20]. However, no work is reported so far for the design of generic odd parity generator. The implementation and metrics of all the existing works reported are summarized in Table 1. The existing designs use back to back three-input Majority Gate, inverter and five-input Majority Voter for carrying out parity generators and they may reduce the effective area and O-Cost of the generators considerably. But it may be mentioned that the structure of five-input Majority Gate is highly susceptible to cell displacement defects of QCA [27-29]. Moreover, the existing layouts of parity generators do not properly follow the design rules of QCA as mentioned in details in Table 1. The long QCA wires are abruptly placed in higher order parity generator layouts and “layout = timing” rule is not properly implemented in parity generator design.
The existing parity generators are solely implemented for the generation of even bit parity. Neither the guidelines nor the layouts of generic odd-parity generators are revealed from these available methodologies. Mostly the use of five-input Majority Gate requires additional three-input Majority Gate which increases the O-Cost and the circuit complexity as well. The “Cost” of five-input Majority Gate based QCA layout has not been analyzed yet. Serious issues in the design of existing parity generator layouts are:
(i) The “layout=timing” problem is not fixed.
(ii) Long QCA wires are placed in higher order parity generator circuits.
The rule for assigning minimum number of QCA cells under single clocking zone is not maintained in most of the cases.
LTEx parity generators
The parity generators designed with LTEx methodology are called the LTEx parity generators. To understand the LTEx methodology, it is necessary to introduce two-input LTEx Module as elaborated below.
Two-input LTEx module
The LTEx module of Fig. 5a, Block diagram includes four Layered T NAND (LT NAND) gates. The LT NAND1 takes two inputs A1 and A0 to produce intermediary output of T1 at clock 0. The inputs A1 and A0 are coupled separately with the intermediary output T1. Then T1 is connected to the input ports of LT NAND2 and LT NAND3 to produce second level intermediary outputs of T2 and T3 respectively at clock 1. These intermediary outputs of T2 and T3 are then given to LT NAND4 to get the final output Z0. The clock signals are applied to quantum cells in order of 0,1,2,3, so that the intermediary outputs get evaluated at clock 3 for proper Exclusive OR output generation. The detailed mathematical interpretations of LTEx block are given by equation (3) as follows:
(3)
Equation (3) is commonly used in LTEx methodology to design even and odd parity generator QCA layouts. The output of the two-input LTEx module is shown in figure 6 Output of two-input LTEx module.
The n-bit even parity generator produces Ex-ORed operation of inputs as P_even = A[n-1] ⊕ A[n-2] ⊕ A[n-3] ⊕ ... ⊕A[2] ⊕A[1] ⊕A[0] and stores it in P_Even. To implement the Ex-ORed addition of such inputs in parity generators, the two-input LTEx modules are required. Primarily, the most significant two bits i.e. A[n-1] and A[n-2] are Ex-ORed by using the first LTEx module. After that the intermediary result is further Ex-ORed with A[n-3] by using second level LTEx module. This process continues till it ends up with the ultimate Ex-OR result of A[1] ⊕A[0] which requires (n-1) number of LTEx modules.
Unlike the even counterparts, the term A[n-1] ⊕ A[n-2] ⊕ A[n-3] ⊕ ... ⊕A[2] ⊕A[1] ⊕A[0] is inverted to form P_odd. Total (n-1) numbers of two-input LTEx modules are used to obtain the expected output of P_odd. The LTEx methodology to generate n-bit even/odd parity generator layouts is given by Algorithm 1:
Algorithm 1: LTEx Methodology:
Step 1: Follow the LTEx expression as follows in expression (3) to find the intermediary result A[i] A[j] LTEx(A[i],A[j])=T_L^+ ((A[i],T_L^+ (A[i],A[j] ),
(A[j],T_L^+ (A[i],A[j])))
where i, j varies from 0-1.
Step 2:
If even parity generator layout is to be generated
then,
P_even=LTEx(A[n-1],LTEx(A[n-1],A[n-2])),...LTEx(A[2], LTEx(A[1], A[0]))
else
P_odd=LTEx(A[n-1],LTEx(A[n-1],A[n-2])), ...LTEx(A[2], LTEx(A[1], A[0]))
According to LTEx methodology, the QCA de-sign parameters such as O-Cost, Costα, Complexity, Irreversible Power Dissipation of even and odd parity generators are modelled in Corollaries 1-8 as provided in Table 2.
IMPLEMENTATION OF N-BIT PARITY GENERATORS USING LTEx METHODOLOGY
Even parity generators
Even and odd Parity Generators are implemented in this sub-section according to the proposed LTEx Methodology. As an example of four-bit even parity generator, the inputs i.e. A3 and A2 are Ex-ORed at the third clock zone to generate the intermediary output as shown in Fig. 5a Block diagram. The EX-ORed output of A3 and A2 is further EX-ORed with A1 at the second level and the second intermittent output is finally Ex-ORed with A0 to produce P_even as demonstrated in Fig. 7a QCA Layouts of LTEx even Parity Generators generated using LTEx Methodology: (a) 4-bit. The QCA layout of four bit parity generator consumes 0.09 µm2 effective area, employs 78 quantum cells and is indicating the O-Cost as 78 and generates P_even with QCA clock delay of 2.25.
Higher orders of even parity generator can also be generated implementing the proposed LTEx methodology. The eight-bit even parity generator of Fig. 6b QCA Layouts of LTEx even Parity Generators generated using LTEx Methodology: (b) 8-bit requires (8-1) =7 two-input LTEx module. Similarly, the 16-bit and 32-bit even LTEx parity generators need (16-1) =15 and (32-1) =31 two-input LTEx module respectively as demonstrated in Fig. 6b-d. In general for the design of n-bit even parity generators, the requirement is (n-1) cascaded two-input LTEx modules.
The O-Cost for 8-bit LTEx parity generator is 26*(8-1) = 182 whereas the 16-bit and 32-bit LTEx parity generators have O-Cost of 26*(16-1) = 390 and 26*(32-1)= 806 respectively. So the O-Cost of 26*(n-1) can be presumed for an n-bit even LTEx parity generator. The value of Costα for four-input layout of Fig. 7a QCA Layouts of LTEx even Parity Generators generated using LTEx Methodology: (a) 4-bit becomes (62+6+32)*2.25=114.75. Similarly the Costα for 8-bit, 16-bit & 32-bit LTEx counterparts of Figs. 7b-d QCA Layouts of LTEx even parity generators generated using LTEx methodology: (b) 8-bit, (c) 16-bit and (d) 32-bit may be counted as (142+14+32)*5.25= 1118.25, (302+30+32)*11.25= 10563.75 & (622+62+32)*22.25= 87108.75 respectively. The generic expression for an n-bit odd parity generator is .
Odd parity generators
It can be observed from LTEx Methodology that inversion of P_even generates P_odd. This observation has made the instantiations of odd parity generator easier. The inverters at the end of the even parity bit QCA layouts do definitely generate odd parity counterparts. The 4-bit, 8-bit, 16-bit and 32-bit QCA odd parity generator’s layouts are demonstrated in Fig. 8(a)-(d) QCA Layouts of LTEx odd Parity Generators generated using LTEx Methodology: (a) 4-bit, (b) 8-bit, (c) 16-bit and (d) 32-bit. The number of LTEx modules for odd parity layouts will remain same as their even counterparts. As two quantum cells are required to invert the even parity output P_even, so the O-Cost values will differ by a count of 2. As an example for 4-bit odd parity layout, the O-Cost becomes 26+2=28 as shown in Fig. 8(a) QCA Layouts of LTEx odd Parity Generators generated using LTEx Methodology: (a) 4-bit. Similar increment of 2 in O-Cost can be observed in 8-bit, 16-bit and 32-bit odd parity layouts and the respective calculations are as follows : (182+2)=184, (390+2)=392 and (806+2)=808. The effective area of 4-bit, 8-bit, 16-bit and 32-bit odd parity generators are reported as 0.08 µm2 , 0.27 µm2, 0.89 µm2 and 3.23 µm2 respectively. The Costα for 4-bit odd parity generator is calculated as (62+7+32)*2.25= 117.
Since an additional inverter is required to invert P_even, so the number of inverter for the 4-bit odd parity generator becomes 6+1=7. The calculations of Costα for 8-bit, 16-bit and 32-bit odd counterparts are calculated as follows: (142+15+32)*5.25= 1155, (302+31+32)*11.25= 10575, (622+63+32)*22.25= 87131 respectively. The generic expression for Costα of an n-bit odd parity generator is .
The irreversible power dissipation for LTEx QCA layouts is modelled as {LT+(I+1)+Cml}. For an n-bit odd parity generator, this factor becomes = (3*n+5). The delays of LTEx even and odd parity generators have similar clock delay of 0.75*(n-1). The Power Delay Products of n-bit even and odd parity generators are as same as (3*n+3)*0.75*(n-1) = 3.75*n-2.25. The QCA design parameters of proposed 4-bit, 8-bit, 16-bit and 32-bit even and odd parity generators are summarized in Table 3.
RESULTS AND DISCUSSION
This work proposes LTEx methodology to implement generic even and odd parity generators by using the Layered T Gate based Exclusive OR Gate [21].The output of two-input LTEx module is verified in Fig. 6 Output of two-input LTEx module. At the falling edge of clock 2, the output Z0 conforms the Ex-OR output. The corollaries 1-8 of LTEx methodology mentioned in Table 2 provide clear ideas about the requirement of LTEx modules, O-Cost, Latency, Costα and Irreversible Power Dissipation during the realization of generic LTEx parity generators. From tables 2 and 3, it can be observed that 4-bit, 8-bit, 16-bit and 32-bit odd LTEx parity generators need 2.56%, 1.09%, 0.51% and 0.24% additional O-Cost respectively than that of their even counterparts.
Comparison of proposed even and odd LTEx parity generators in terms of effective area in µm2 shows respective increase of 9.45%, 3.37%, 14.10% and 4.83% in 4-bit, 8-bit, 16-bit and 32-bit odd LTEx parity generator’s respective area compared to their even counterparts. The Costα for 4-bit, 8-bit, 16-bit and 32-bit odd LTEx parity generators are 2.63%, -3.19%, 0.106% and 0.0255% higher than that of their even LTEx counterparts as reported in the table 3. The 4-bit, 8-bit, 16-bit and 32-bit odd LTEx parity generators consume 6.67%, 3.70%, 1.96% and 1.01% respective higher power compared to their even LTEx counterparts as summarized in table 3. As the LTEx modules are using a single additional layer, so the complexity becomes 3 for the proposed LTEx layouts.
The proposed 4-bit, 8-bit, 16-bit and 32-bit even LTEx parity generators are compared with the existing designs of [14-20] in terms of O-Cost, Effective Area in nm2, Costα and Irreversible Power Dissipation. The 4-bit LTEx parity generator requires 10.34% less O-Cost than the optimized 4-bit Singh parity generator counterpart [17]. The 4-bit LTEx parity generator consumes sharp 24% less effective area than the Singh counterpart [17] and Sasamal counterpart [19]. Till date, the 4-bit Hashemi parity generator [14] has been reported as the best design in terms of Costα and Irreversible Power Dissipation. However the Costα for 4-bit LTEx parity generator is counted as 114.75 in Table 4 whereas the value becomes 220 for the Hashemi parity generator [14]. On the other hand, the Irreversible Power Dissipation becomes 16 for the former parity generator [14]. Hence sharp 47.84% reduced value of Costα and 6.25% less power consumption in comparison to Hashemi 4-bit parity generator [14] can be noted from Table 4.
The 8-bit LTEx parity generator requires 14.56% less O-Cost and 11% reduced effective area as compared to 8-bit Singh parity generator design [17]. Like the 4-bit LTEx Parity Generator, the 8-bit LTEx parity generator also has 38.42% less Costα and ~20.6% reduced Power consumption as compared to the Hashemi 8-bit parity generator [14] as shown in Table 4.
In case of the 16-bit parity generator design, the proposed QCA layout has 18.75% less O-Cost and it covers 0.25% less effective area than its competitor, namely the Singh parity generator [17] and Sasamal counterpart [19]. The 16-bit LTEx parity generator has become favourable due to its 2.13% lesser Costα and 32.9 % reduced power consumption than Hashemi counterpart [14] as summarized in Table 4. The 32-bit Singh parity generator has best QCA design metrics in terms of its O-Cost and effective area among the Anghizi parity generator [15], the Sheikhfaal parity generator [16] and the Hashemi parity generator [14] because this generator employs the design of Ex-OR Gate with five-input Majority Voters in the high fan-in QCA layouts. The successful instantiation of the 32-bit LTEx parity generator makes it better even compared to Singh counterpart [17]. The 32-bit LTEx parity generator leads by 22.8% O-Cost and 0.49% effective area than Singh parity counterpart [17]. Moreover the 32-bit LTEx parity generator consumes 33.29% less irreversible power than Anghizi parity generator [15].
A.N. Bahar et al. [18] have proposed another five-input Majority Voter based even parity generators. The Bahar parity generator needs additional interconnects because the input and outputs are placed inside the inner part of the QCA layouts. Hence the design rule of QCA is not followed. The corner cells of five-input Majority Gates are highly sensitive to QCA defects like Cell Displacement defect, Cell Misalignment defect and Rotational cell defects [27-29]. In addition, the formulation of ≠ 2 -bit Bahar parity generator using five-input Majority Gate is critical. Due to these serious issues, this work excludes the parameters of Bahar parity generator from the evaluation of proposed LTEx parity generators. It is thus evident that the LTEx methodology clearly estimates the requirements of LTEx module, delay, O-Cost, Costα, Irreversible Power Dissipation of generic even, and odd LTEx parity generators Table 2 whereas, the previous designs neither proposed odd parity generator nor provide such estimations of n-bit parity generators as the best of author’s knowledge. Though LTEx parity generators show high delay compared to the existing designs, still the proposed parity generators excel in cost function as shown in table 4. Moreover the proposed layouts have the following features:
(i) The input-output cells are placed at the border of the layouts to avoid unnecessary delay.
(ii) Minimum two cells are clocked together to ensure the proper dataflow through the circuit.
(iii) The use of QCA cells with +1/-1 orientation makes the layouts more stable [30].
The fabrication of two-input LTEx module can be done by biplanar alternative cells [11]. As biplanar alternative cells are not true three-dimensional structure, so the complexity of fabrication of three-dimensional structure can be taken aside. The upper layer cells of Fig. 5(b) QCA Layout of Two-input LTEx module can be implemented by rotated cell using two-dimensional electron gases. Moreover, in terms of QCA design metrics the biplanar approach of the proposed layouts makes the methodology effective.
The outputs of LTEx parity generators have been demonstrated in Fig. 9(a)-(h) Output of even parity generator (a) 4-bit, (c) 8-bit, (e) 16-bit, (g) 32-bit and odd parity generator (b) 4-bit, (d) 8-bit, (f) 16-bit, (h) 32-bit. The outputs of proposed LTEx parity generator layouts are producing the necessary result at clock 0. Hence the falling edge of clock 0 plays pivotal role in obtaining the proper output as demonstrated by using rectangular box in the Fig. 9(a)-(d). Similar case studies are also observed for 16-bit and 32-bit parity generator’s outputs.
CONCLUSION
In this work, a new LTEx methodology is introduced which generates n-bit even and odd Parity generators. As the proposed algorithm uses two-input LTEx Module, the implemented parity generators are termed as LTEx parity generators. The significant contribution of this approach of LTEx methodology is the reduction of O-Cost, Effective Area, Costα and Irreversible Power Dissipation of QCA parity generator layouts. The even and odd parity generator layouts of different word sizes (i.e. 4, 8, 16 and 32) are generated by using well-known computer aided design tool QCADesigner. These layouts are compared with the existing designs for continuous research and development. Recurring and dynamic analysis of the comparative results may be significant for extending future research on this area.
CONFLICT OF INTEREST
The authors declare that there is no conflict of interests regarding the publication of this manuscript.
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