Improved drain current characteristics of tunnel field effect transistor with heterodielectric stacked structure

Document Type : Reasearch Paper

Authors

• Vimala Palanichamy ¹
• Netravathi Kulkarni ²
• Arun Samuel Thankamony Sarasam ³

¹ Associate Professor, Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India.

² PG Scholar, Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India.

³ Associate Professor, Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamilnadu, India.

Abstract

In this paper, we proposed a 2-D analytical model for electrical characteristics such as surface potential, electric field and drain current of Silicon-on-Insulator Tunnel Field Effect Transistor (SOI TFETs) with a SiO₂/High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel region potential. The modeled channel potential is to calculate both vertical and lateral electric field.  2-D Kane’s model is used to calculate the drain current of TFET and the expression is taken out by analytically integrating the band-to-band tunneling generation rate over the thickness of channel region. The device is modeled in variation with different device parameters like channel length (L_CH), dielectric thickness (t_ox), silicon thickness (t_si) and input voltage (V_ds and V_gs). Also, the comparison of SiO₂ and stacked high k dielectric TFET is obtained. It has been found from the presented results that the hetero-dielectric stacked TFET structure provides ON current 10^-6A/um. However, SiO₂ dielectric structure provides the ON current of 10^-8A/um. The proposed model is validated by comparing it with Technology Computer-Aided Design (TCAD) simulation results obtained by using SILVACO ATLAS device simulation software.

Keywords

• Analytical Modeling
• High-k Dielectric
• Poisson’s Equation
• Superposition Principle
• Tunnel FET (TFET)

20.1001.1.20088868.2019.10.4.6.3

Main Subjects

• Nanosemiconductor Device Modelling

---

References

[1]       Choi W.Y., Park B.G., Lee J. D., Liu T. J. K., (2007), Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60mV dec. IEEE Elec. Dev. Lett. 28: 743–745.

[2]       Zhang Q., Zhao W., Seabaugh A., (2006), Low-subthreshold-swing Tunnel Transistors.  IEEE Elec. Dev. Lett. 27: 297–300.

[3]       Vimala P., Balamurugan N. B., (2013), Modelling the centroid and charge density in double-gate MOSFETs including quantum effects. Int. J. Elect.100: 1283-1295.

[4]       Vimala P., Balamurugan N. B., (2014), New analytical model for nanoscale tri-gate SOI MOSFETs including quantum effects. IEEE J. Elec. Dev. Soc. 2: 1-7.

[5]       Choi W. Y., Song J. Y., Lee J. D., Park Y. J., Park B.-G., (2005), 100-nm n-/p-channel I-MOS using a novel self-aligned structure. IEEE Elect. Dev. Lett. 26: 261–263.

[6]       Kam H., Lee D. T., Howe R. T., King T.-J., (2005), Negative capacitance tunnel field effect transistor: A novel device with low subthreshold swing and high ON current. IEDM Tech. Dig. 8: 463–466.

[7]       Abele N., Fritschi N., Boucart K., Casset F., Ancey P., Ionescu A. M., (2005), Negative capacitance tunnel field effect transistor: A novel device with low subthreshold swing and high ON current . IEDM Tech. Dig. 8: 1075–1077.

[8]       Wang P.-F., Hilsenbeck K., Nirschl T., Oswald M., Stepper C., Weiss M., (2004), Complementary tunneling transistor for low power application. Solid State Elect. 48: 2281–2286.

[9]     Choi W. Y., Song J. Y., Lee J. D., Park Y. J., Park B.-G., (2005), 70-nm impact tunneling field-effect transistors (TFETs). IEDM Tech. Dig. 8: 975–978.

[10]   Boucart K., Ionescu A. M., (2007), Double-gate tunnel FET with high-gate dielectric. IEEE Trans. Elec Dev. 54: 1725-1733.

[11]  Kumar S., Goel E., Singh K., Singh B., Kumar M., Jit S., (2016), A compact 2-D analytical model for electrical characteristics of double-gate Tunnel-FETs with a SiO2/High-k stacked gate-oxide structure. IEEE Trans. Elec. Dev. 60: 3291–3299.

[12]  Chiang T. K., Chen M. L., (2007), Analytical modeling of a triple material double gate TFET with hetero-dielectric gate stack. Solid-State Elec. 51: 387–393.

[13]  Rupam G., Brinda B., (2017), An analytical model of drain current in a nanoscale circular gate. IEEE Tran. Ele. Dev. 64: 45-51.

[14]  Jiang S. Y., Yuan Y., Wang X., Chen L., Zhu H., Sun Q. Q., Zhang D. W., (2018), A semi-floating gate transistor with enhanced embedded tunneling field-effect transistor. IEEE Tran. Ele. Dev. 39: 1497-1499.

[15]   Lee M. J., Choi W. Y., (2011), Analytical model of a single-gate silicon-on-insulator (SOI) tunneling field effect transistors (TFETs). Solid State Elec. 63: 110-114.

[16]  Kane E. O., (1960), Zener tunneling in Semiconductors. J. Phys. Chem. Solids. 12: 181–188.