Conventional vs. junctionless gate-stack DG-MOSFET based CMOS inverter

Document Type : Reasearch Paper

Authors

• Shubham Tayal ¹
• Pachimatla Samrat ²
• Vadula Keerthi ²
• Biswajit Jena ³
• Karthik Rajendra ⁴

¹ Department of Electronics & Communication Engineering, Sree Dattha Institute of Engineering and Science, Telangana, India.

² Department of ECE, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.

³ Department of ECE, Koneru Lakshmaiah Education Foundation, Amaravati nehi Vaddeswaram, India.

⁴ Department of Electronics and Communication Engineering, MLR Institute of Technology, Hyderabad, Telangana, India.

10.22034/ijnd.2021.677807

Abstract

In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO₂ is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (ΔNM_L), high noise margin (ΔNM_H), gain (ΔA) & propagation delay (Δp < sub>d) is 3.19%, 1.64%, 5.2% & 0.9% respectively when SiO₂ is replaced by TiO₂ at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is 1.96%, 1.24%, 3.4% & 1.71% respectively in case of JL-DG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter.

Keywords

• CMOS Inverter
• DG-MOSFET
• Gate-Stack
• High-k
• Junctionless

20.1001.1.20088868.2021.12.2.2.9

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