[1] Moore G. E., (2006), Cramming more components onto integrated circuits. IEEE Solid-State Circuits Lett.11: 33-35.
[2] Hopkinson M., (2015), With silicon pushed to its limits, what will power the next electronics revolution? available online: https://phys.org/news/2015-08-silicon-limits-power-electronics-revolution.html.
[3] “International technology roadmap for semiconductors,” (2007), http://www.itrs.net.
[4] Kuhn K. J., (2011), CMOS scaling for the 22 nm node and beyond: Device physics and technology. Proc. Int. Symp. VLSI Technol. Syst. App.
[5] Roy K., Mukhopadhyay S., Mahmoodi-Meimand H., (2003), Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE. 91: 305-327.
[6] Frank D. J., Dennard R. H., Nowak E., Solomon P. M., Taur Y., Hon-Sum Philip W., (2001), Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE.89: 259-288.
[7] Chenming H., (1996), Gate oxide scaling limits and projection. Tech. Dig. Int. Electron. Dev. Mtg. 0-7803-3393.
[8] Yee-Chia Y., Tsu-Jae K., Chenming H., (2003), MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans. Electron Devices.50: 1027-1035.
[9] Chen J., Chan T. Y., Chen I. C., Ko P. K., Hu C., (1987), Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. 8: 515-517.
[10] “International technology roadmap for semiconductors,” (2011), http://www.itrs.net.
[11] Skotnicki T., Hutchby J. A., Tsu-Jae K., Wong H. P., Boeuf F., (2005), The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance.IEEE Circuits Dev. Mag. 21: 16-26.
[12] Wong H. P., Frank D. J., Solomon P. M., (1998), Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation. International Electron Devices Meeting. Technical Digest (Cat. No.98CH36217).
[13] Solomon P. M., Guarini K. W., Zhang Y., Chan K., Jones E. C., Cohen G. M., Krasnoperova A., Ronay M., Dokumaci O., Hovel H. J., Bucchignano J. J., Cabral C., Lavoie C., Ku V., Boyd D. C., Petrarca K., Yoon J. H., Babich I. V., Treichler J., Kozlowski P. M., Newbury J. S., Emic C. P. D., Sicina R. M., Benedict J., Wong H. P., (2003), Two gates are better than one [double-gate MOSFET process]. IEEE Circuits Devices Mag. 19: 48-62.
[14] Suzuki K., Tanaka T., Tosaka Y., Horie,H., Arimoto Y., (1993), Scaling theory for double-gate SOI MOSFET's. IEEE Trans. Electron Devices.40: 2326-2329.
[15] Nowak E. J., Aller I., Ludwig T., Kim K., Joshi R. V., Ching-Te C., Bernstein K., Puri R., (2004), Turning silicon on its edge [double gate CMOS/FinFET technology]. IEEE Circuits Devices Mag. 20: 20-31.
[16] Salahuddin S. M., Shaik K. A., Gupta A., Chava B., Gupta M., Weckx P., Ryckaert J., Spessot A. (2019). SRAM with buried power distribution to improve write margin and performance in advanced technology nodes. IEEE Electron Device Lett. 40: 1261-1264.
[17] A Project funded by
MHRD, Govt. of India, (2021), https://nptel.iitm.ac.in.
[18] Xie Q., Xu J., Taur Y., (2012), Review and critique of analytic models of MOSFET short-channel effects in subthreshold. IEEE Trans. Electron Devices. 59: 1569-1579.
[19] Girish H., Shashikumar D., (2016), Insights of performance enhancement techniques on FinFET-based SRAM cells. Commun. Appl. Electron. 5: 20-26.
[20] Agarwal A., Mukhopadhyay S., Kim C. H., Raychowdhury A., Roy K., (2005), Leakage power analysis and reduction: Models, estimation and tools. IEE Proc Comput Digit Tech. 152: 353-368.
[21] Islam A., Hasan M., (2012), Leakage characterization of 10T SRAM Cell. IEEE Trans. Electron Dev. 59: 631-638.
[22] He Y., Zhang J., Wu X., Si X., Zhen S., Zhang B., (2019), A half-select disturb-free 11T SRAM cell with built-in write/read-assist scheme for ultralow-voltage operations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27: 2344-2353.
[23] Chang L., Fried D. M., Hergenrother J., Sleight J. W., Dennard R. H., Montoye R. K., Sekaric L., McNab S. J., Topol A. W., Adams C. D., Guarini K. W., Haensch W., (2005), Stable SRAM cell design for the 32 nm node and beyond. Tech. Dig. Symp. VLSI Tech.
[24] Chang I. J., Kim J., Park S. P., Roy K., (2009), A 32 kb 10T Sub-Threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. IEEE J. Solid-State Circuits.44: 650-658.
[25] Chang M., Chiu Y., Hwang W., (2012), Design and Iso-Area analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS. IEEE Trans. Circuits Syst., II, Exp. Briefs. 59: 429-433.
[26] Chien Y., Wang J., (2018). A 0.2 V 32-Kb 10T SRAM with 41 nW standby power for IoT applications. IEEE Trans. Circuits Syst. I, Reg. Papers. 65: 2443-2454.
[27] Chiu Y., Hu Y., Tu M., Zhao J., Jou S., Chuang C., (2013), A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. Int. Symp. Low Pwr Electron. Design.
[28] Wen L., Zhang Y., Zeng X., (2019), Column-selection-enabled 10T SRAM utilizing shared Diff-VDD write and dropped-VDD read for power reduction. IEEE Trans. Very Large Scale Integr.(VLSI) Syst. 27: 1470-1474.
[29] Torrens G., Alorda B., Carmona C., MalagÓn-PeriÁnez D., Segura J., Bota S., (2019), A 65-nm reliable 6T CMOS SRAM cell with minimum size transistors. IEEE Trans. Emerg. Topics Comput. 7: 447-455.
[30] Grover A., Visweswaran G. S., Parthasarathy C. R., Daud M., Turgis D., Giraud B., Noel J., Miro-Panades I., Moritz G., Beigné E., Flatresse P., Kumar P., Azmi S., (2017), A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz bit-interleaved SRAM with 8 T SRAM cell and data dependent write assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I, Reg. Papers.64: 2438-2447.
[31] Pasandi G., Fakhraie S. M., (2014), An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs. IEEE Trans. Electron Dev.61: 2357-2363.
[32] Hisamoto D., Kaga T., Kawamoto Y., Takeda E., (1989), A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET. Tech. Dig. Int. Electron Dev. Mtg.
[33] Hisamoto D., Wen-Chin L., Kedzierski J., Takeuchi H., Asano K., Kuo C., Anderson E., Tsu-Jae K., Bokor J., Chenming H., (2000), FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Dev.47: 2320-2325.
[34] Bin Y., Leland C., Ahmed S., Haihong W., Bell S., Chih-Yuh Y., Tabery C., Chau H., Qi X., Tsu-Jae K., Bokor J., Chenming H., Ming-Ren L., Kyser D., (2002), FinFET scaling to 10 nm gate length. Tech. Dig. Int. Electron Dev. Mtg.
[35] Tang S. H., Chang L., Lindert N., Yang-Kyu C., Wen-Chin L., Xuejue H., Subramanian V., Bokor J., Tsu-Jae K., Chenming H., (2001), FinFET-a quasi-planar double-gate MOSFET. Dig. Tech. Pap. IEEE Int. Solid State Circuits Conf.
[36] Guillorn M., Chang J., Bryant A., Fuller N., Dokumaci O., Wang X., Newbury J., Babich K., Ott J., Haran B., Yu R., Lavoie C., Klaus D., Zhang Y., Sikorski E., Graham W., To B., Lofaro M., Tornello J., Haensch W., (2008), FinFET performance advantage at 22nm: An AC perspective. Symp. VLSI Technol.
[37] Fu-Liang Y., Di-Hong L., Hou-Yu C., Chang-Yun C., Sheng-Da L., Cheng-Chuan H., Tang-Xuan C., Hung-Wei C., Chien-Chao H., Yi-Hsuan L., Chung-Cheng W., Chi-Chun C., Shih-Chang C., Ying-Tsung C., Ying-Ho C., Chih-Jian C., Bor-Wen C., Peng-Fu H., Jyu-Horng S., Han-Jan T., Yee-Chia Y., Yiming L., Jam-Wem L., Pu C., Mong-Song L., Chenming H., (2004), 5nm-gate nanowire FinFET. Dig. Tech. Pap. Symp. VLSI Tech.
[38] Xuejue H., Wen-Chin L., Charles K., Hisamoto D., Leland C., Kedzierski J., Anderson E., Takeuchi H., Yang-Kyu C., Asano K., Subramanian V., Tsu-Jae K., Bokor J., & Chenming H., (1999), Sub 50-nm FinFET: PMOS. Tech. Dig. Int. Electron Dev. Mtg.
[39] Intel’s Revolutionary 22nm Transistor Technology, May 2011. http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-detailspresentation.pdf.
[40] Zimpeck A. L., Meinhardt C., Posser G., Reis R., (2016), FinFET cells with different transistor sizing techniques against PVT variations. IEEE Int. Symp. Circuits Syst.
[41] Joshi R. V., Ziegler M. M., Wetter H., (2017), A low voltage SRAM using resonant supply boosting. IEEE J. Solid-State Circuits. 52: 634-644.
[42] Joshi R. V., Ziegler M., Wetter H., Wandel C., Ainspan H., (2015), 14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. Symp. VLSI Circuits.
[43] Song T., Rim W., Park S., Kim Y., Yang G., Kim H., Baek S., Jung J., Kwon B., Cho S., Jung H., Choo Y., Choi J., (2017), A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization. IEEE J. Solid-State Circuits.52: 240-249.
[44] Kang K., Jeong H., Yang Y., Park J., Kim K., Jung A.-O., (2015), Full-swing local bitline SRAM architecture based on the 22-nm FinFET technology for low-voltage operation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24: 1-1.
[45] Sinangil M. E., Lin Y., Liao H. J., Chang J., (2018), A 290MV ultra-low voltage one-port SRAM compiler design using a 12T write contention and read upset free bit-cell in 7NM FinFET technology. IEEE Symp. VLSI Circuits.
[46] Turi M. A., Delgado-Frias J. G., (2020), Effective low leakage 6T and 8T FinFET SRAMs: Using cells with reverse-biased FinFETs, near-threshold operation, and power gating. IEEE Trans. Circuits Syst. II, Exp. Briefs.67: 765-769.
[47] Sun J., Li X., Sun Y., Shi Y., (2020), Impact of geometry, doping, temperature, and boundary conductivity on thermal characteristics of 14-nm bulk and SOI FinFETs. IEEE Trans. Device Mater. Rel. 20: 119-127.
[48] Kam H., (2014), A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size. Proc. IEEE IEDM.
[49] Lin C., Greene B., Narasimha S., Cai J., Bryant A., Radens C., Narayanan V., Linder B., Ho H., Aiyar A., Alptekin E., An J., Aquilino M., Bao R., Basker V., Breil N., Brodsky M., Chang W., Clevenger L., Chidambarrao D., Christiansen C., Conklin D., DeWan C., Dong H., Economikos L., Engel B., Fang S., Ferrer D., Friedman A., Gabor A., Guarin F., Guan X., Hasanuzzaman M., Hong J., Hoyos D., Jagannathan B., Jain S., Jeng S., Johnson J., Kannan B., Ke Y., Khan B., Kim B., Koswatta S., Kumar A., Kwon T., Kwon U., Lanzerotti L., Lee H., Lee W., Levesque A., Li W., Li Z., Liu W., Mahajan S., McStay K., Nayfeh H., Nicoll W., Northrop G., Ogino A., Pei C., Polvino S., Ramachandran R., Ren Z., Robison R., Saraf I., Sardesai V., Saudari S., Schepis D., Sheraw C., Siddiqui S., Song L., Stein K., Tran C., Utomo H., Vega R., Wang G., Wang H., Wang W., Wang X., Wehelle-Gamage D., Woodard E., Xu Y., Yang Y., Zhan N., Zhao K., Zhu C., Boyd K., Engbrecht E., Henson K., Kaste E., Krishnan S., Maciejewski E., Shang H., Zamdmer N., Divakaruni R., Rice J., Stiffler S., Agnello P., (2014), High performance 14 nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization. IEEE Int Electron Dev Mtg.
[50] Giterman R., Shalom A., Burg A., Fish A., Teman A., (2020), A 1-Mbit fully logic-compatible 3T gain-cell embedded DRAM in 16-nm FinFET. IEEE Solid-State Circuits Lett. 3: 110-113.
[51] Cho K., Park J., Oh T. W., Jung S.-O., (2020), One-sided schmitt-trigger-based 9T SRAM cell for near-threshold operation. IEEE Trans. Circuits Syst. I, Reg. Papers. 67: 1551-1561.
[52] Huo Q., Wu Z., Wang X., Huang W., Yao J., Bu J., Zhang F., Li L., Liu M., (2020), Physics-based device-circuit cooptimization scheme for 7-nm technology node SRAM design and beyond. IEEE Trans. Electron Dev.67: 907-914.
[53] Sinha S. K., Chaudhury S., (2013), Impact of Oxide thickness on gate capacitance-a comprehensive analysis on MOSFET, nanowire FET, and CNTFET devices. IEEE Trans. Nanotechnol. 12: 958-964.
[54] Kumar G., Singh A., Raj B., (2018), Design and analysis of a gate-all-around CNTFET-based SRAM cell. J. Comput. Electron.17: 138-145.
[55] Dresselhaus M. S., Dresselhaus G., Saito R., (1992), Carbon fibers based on C60 and their symmetry. Phys. Rev. B. Condens Matter.45: 6234-6242.
[56] Nano HUB Tools [Online]. Available: www.nanohub.org.
[57] Li T., Xie F., Liang X., Xu Q., Chakrabarty K., Jing N., Jiang L., (2016), A novel test method for metallic CNTs in CNFET-based SRAMs. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 35: 1192-1205.
[58] Ahmed Z., Zhang L., Sarfraz K., Chan M., (2016), Modeling CNTFET performance variation due to spatial distribution of carbon nanotubes. IEEE Trans. Electron Devices.63: 3776-3781.
[59] Tura A., Woo J. C. S., (2010), Performance comparison of silicon steep subthreshold FETs. IEEE Trans. Electron Dev.57: 1362-1368.
[60] Chen Y., Fan M., Hu V. P., Su P., Chuang C., (2013), Design and analysis of robust tunneling FET SRAM. IEEE Trans. Electron Dev. 60: 1092-1098.
[61] Strangio S., Palestri P., Esseni D., Selmi L., Crupi F., Richter S., Zhao Q., Mantl S., (2015), Impact of TFET unidirectionality and ambipolarity on the performance of 6T SRAM cells. IEEE J. Electron Dev. Soc. 3: 223-232.
[62] Knoll L., Zhao Q., Nichau A., Trellenkamp S., Richter S., Schäfer A., Esseni D., Selmi L., Bourdelle K. K., Mantl S., (2013), Inverters with Strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Dev. Lett. 34: 813-815.
[63] Richter S., Schulte-Braucks C., Knoll L., Luong G. V., Schäfer A., Trellenkamp S., Zhao Q., Mantl S., (2014), Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V. 72nd Device Research Conf.
[64] Agrawal N., Liu H., Arghavani R., Narayanan V., Datta S., (2015), Impact of variation in nanoscale silicon and non-silicon FinFETs and tunnel FETs on device and SRAM performance. IEEE Trans. Electron Dev.62: 1691-1697.
[65] Chang M., Chang S., Chou P., Wu W., (2011), A 130 mV SRAM with expanded write and read margins for subthreshold applications. IEEE J. Solid-State Circuits.46: 520-529.
[66] Farkhani H., Peiravi A., Moradi F., (2015), A new write assist technique for SRAM design in 65nm CMOS technology. Integration. 50: 16-27.
[67] Yamaoka M., Osada K., Tsuchiya R., Horiuchi M., Kimura S., Kawahara T., (2004), Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology. Dig. Tech. Pap. Symp. VLSI Tech.
[68] Kumar R., Pattanaik M., Shukla N., (2012), Characterization of a novel low-power SRAM bit-cell structure at deep sub-micron CMOS technology for multimedia applications. Circuits and Systems. 3: 23-28.
[69] Razavipour G., Afzali-Kusha A., Pedram M., (2009), Design and analysis of two low-power SRAM cell structures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17: 1551-1555.
[70] Teman A., Mordakhay A., Mezhibovsky J., Fish A., (2012), A 40-nm sub-threshold 5T SRAM bit cell with improved read and write stability. IEEE Trans. Circuits Syst., II, Exp. Briefs. 59: 873-877.
[71] Ahmad S., Gupta M. K., Alam N., Hasan M., (2016), Single-ended schmitt-trigger-based robust low-power SRAM cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.24: 2634-2642.
[72] Lee Y., Park G.-H., Choi B., Yoon J., Kim H.-J., Kim T., Kim D. M., Kang M.-H., Choi S.-J., (2020), Design study of the gate-all-around silicon nanosheet MOSFETs. Semicond. Sci. Technol.35: 41-46.
[73] Lin Y., Cheng C., Jhan Y., Kurniawan E. D., Du Y., Lin Y., Wu Y., (2018), Hybrid P-channel/N-substrate Poly-Si nanosheet junctionless field-effect transistors with trench and gate-all-around structure. IEEE Trans. Nanotechnol.17: 1014-1019.
[74] Endo K., uchi S. O., Ishikawa Y., Liu Y., Matsukawa T., Sakamoto K., Masahara M., Tsukada J., Ishii K., Yamauchi H., Suzuki E., (2009), Independent-double-gate FinFET SRAM for leakage current reduction. IEEE Electron Dev. Lett.30: 757-759.
[75] Bansal A., Mukhopadhyay S., Roy K., (2007), Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale Era. IEEE Trans. Electron Dev.54: 1409-1419.
[76] Waffle F., Salehuddin F., Mohd Zain A. S., Kaharudin K. E., Haroon H., Razak H., Idris S., baharudin zamani Z., Maheran A., (2018), 30 nm DG-FinFET 3D construction impact towards short channel effects. Indones. J. Electr. Eng. Comput. Sci. 12: 1358-1365.
[77] Nawaz M., Molzer W., Decker S., Giles L.-F., Schulz T., (2007), On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation with 3D TCAD. Microelectronics J.38: 1238-1251.
[78] Nawaz M., Molzer W., Haibach P., Landgraf E., Roesner W., Staedele M., Luyken H., Gencer A., (2006), Validation of 30 nm process simulation using 3D TCAD for FinFET devices. Semicond. Sci. Technol.21: 1111-1117.
[79] Zhang Z., Jiang X., Wang R., Guo S., Wang Y., Huang R., (2018), Extraction of process variation parameters in FinFET technology based on compact modeling and characterization. IEEE Trans. Electron Dev. 65: 847-854.
[80] Fan M., Wu Y., Hu V. P., Hsieh C., Su P., Chuang C., (2011), Comparison of 4T and 6T FinFET SRAM cells for subthreshold operation considering variability-A model-based approach. IEEE Trans. Electron Dev.58: 609-616.
[81] Kerber P., Kanj R., Joshi R. V., (2013), Strained SOI FINFET SRAM design. IEEE Electron Dev. Lett.34: 876-878.
[82] Oh T. W., Jeong H., Kang K., Park J., Yang Y., Jung S., (2017), Power-gated 9T SRAM cell for low-energy operation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.25: 1183-1187.
[83] Saxena S., Mehra R., (2017), Low-power and high-speed 13T SRAM cell using FinFETs. IET Circ. Dev. Syst. 11: 250-255.
[84] Yang Y., Park J., Song S. C., Wang J., Yeap G., Jung S., (2015), Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.23: 2748-2752.
[85] Ebrahimi B., Afzali-Kusha A., Mahmoodi H., (2014), Robust FinFET SRAM design based on dynamic back-gate voltage adjustment. Microelectron Reliab.54: 2604-2612.
[86] Carlson A., Guo Z., Balasubramanian S., Zlatanovici R., Liu T. K., Nikolic B., (2010), SRAM read/write margin enhancements using FinFETs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.18: 887-900.
[87] Park J., Yang Y., Jeong H., Song S. C., Wang J., Yeap G., Jung S., (2015), Design of a 22-nm FinFET-based SRAM with read Buffer for Near-Threshold Voltage Operation. IEEE Trans. Electron Dev. 62: 1698-1704.
[88] Ansari M., Afzali-Kusha H., Ebrahimi B., Navabi Z., Afzali-Kusha A., Pedram M., (2015), A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies. Integration.50: 91-106.
[89] Yang Y., Jeong H., Song S. C., Wang J., Yeap G., Jung S., (2016), Single Bit-Line 7T SRAM cell for near-threshold voltage operation with enhanced performance and energy in 14 nm FinFET technology. IEEE Trans. Circuits Syst. I, Reg. Papers.63: 1023-1032.
[90] Guler A., Jha N. K., (2019), Three-dimensional monolithic FinFET-based 8T SRAM cell design for enhanced read time and low leakage. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27: 899-912.
[91] Pal P. K., Kaushik B. K., Dasgupta S., (2014), Design metrics improvement for SRAMs using symmetric dual- $k$ spacer (SymD-$k$) FinFETs. IEEE Trans. Electron Devices.61: 1123-1130.
[92] Zheng P., Connelly D., Ding F., Liu T. K., (2015a), FinFET evolution toward stacked-nanowire FET for CMOS technology scaling. IEEE Trans. Electron Devices.62: 3945-3950.
[93] Zheng P., Connelly D., Ding F., Liu T. K., (2015b), Simulation-based study of the inserted-oxide FinFET for future low-power system-on-chip applications. IEEE Electron Dev. Lett.36: 742-744.
[94] Akkala A. G., Venkatesan R., Raghunathan A., Roy K., (2016), Asymmetric underlapped sub-10-nm n-FinFETs for high-speed and low-leakage 6T SRAMs. IEEE Trans. Electron Dev.63: 1034-1040.
[95] Jaksic Z., Canal R., (2013), Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations. IEEE Trans. Electron Dev.60: 49-55.
[96] Zhang X., Connelly D., Zheng P., Takeuchi H., Hytha M., Mears R. J., Liu T. K., (2016), Analysis of 7/8-nm Bulk-Si FinFET technologies for 6T-SRAM scaling. IEEE Trans. Electron Dev.63: 1502-1507.
[97] Zhang X., Connelly D., Takeuchi H., Hytha M., Mears R., King Liu T.-J., (2016), Comparison of SOI versus bulk FinFET technologies for 6T-SRAM voltage scaling at the 7-/8-nm node. IEEE Trans. Electron Dev. 64: 329-332.
[98] Mann R. W., Zhao M., Parihar S., Gao Q., Arya A., Radens C., Pandey S. M., Versaggi J., Higman J. M., Carter R., (2019), An extrinsic device and leakage mechanism in advanced bulk FinFET SRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.27: 1819-1827.
[99] Kanhaiya P. S., Lau C., Hills G., Bishop M. D., Shulaker M. M., (2019), Carbon nanotube-based CMOS SRAM: 1 kbit 6T SRAM arrays and 10T SRAM cells. IEEE Trans. Electron Dev. 66: 5375-5380.
[100] You K., Nepal K., (2011), Design of a ternary static memory cell using carbon nanotube-based transistors. Micro Nano Lett. 6: 381-385.
[101] Zhang Z., Delgado-Frias J. G., (2012), Carbon nanotube SRAM design with metallic CNT or removed metallic CNT tolerant approaches. IEEE Trans. Nanotechnol. 11: 788-798.
[102] Zhang Z., Delgado-Frias J. G., (2014), Near-threshold CNTFET SRAM cell design with word-line boosting and removed metallic CNT tolerance. IEEE Trans. Nanotechnol. 13: 182-191.
[103] Liu J., Clavel M. B., Hudait M. K., (2017), An energy-efficient tensile-strained Ge/InGaAs TFET 7T SRAM cell architecture for ultralow-voltage applications. IEEE Trans. Electron Dev. 64: 2193-2200.
[104] Makosiej A., Gupta N., Vladimirescu A., Vakul N., Cotofana S., Mahapatra S., Anghel C., Amara A., (2016), Ultra-low leakage SRAM design with sub-32nm tunnel FETs for low standby power applications. Micro Nano Lett.11: 828-831.
[105] Pown M., Lakshmi B., (2020), Investigation of radiation hardened TFET SRAM cell for mitigation of single event upset. IEEE J. Electron Dev. Soc. 8: 1397-1403.
[106] Chen Y., Fan M., Hu V. P., Su P., Chuang C., (2014), Evaluation of stability, performance of ultra-low voltage MOSFET, TFET, and mixed TFET-MOSFET SRAM cell with write-assist circuits. IEEE J. Emerg. Sel. Topics Circuits Syst.4: 389-399.
[107] Amir M. F., Trivedi A. R., Mukhopadhyay S., (2016), Exploration of Si/Ge tunnel FET bit cells for ultra-low power embedded memory. IEEE J. Emerg. Sel. Topics Circuits Syst. 6: 185-197.
[108] Peng C., Yang Z., Lin Z., Wu X., Li X., (2021), Reverse bias current eliminated, read-separated, and write-enhanced tunnel FET SRAM. IEEE Trans. Circuits Syst., II, Exp. Briefs.68: 466-470.
[109] Mohammed M. U., Chowdhury M. H., (2018), Reliability and energy efficiency of the tunneling transistor-based 6T SRAM cell in sub-10 nm domain. IEEE Trans. Circuits Syst., II, Exp. Briefs.65: 1829-1833.
[110] Luong G. V., Strangio S., Tiedemann A. T., Bernardy P., Trellenkamp S., Palestri P., Mantl S., Zhao Q. T., (2018), Strained silicon complementary TFET SRAM: Experimental demonstration and simulations. IEEE J. Electron Dev. Soc. 6: 1033-1040.
[111] Ahmad S., Ahmad S. A., Muqeem M., Alam N., Hasan M., (2019), TFET-Based robust 7T SRAM cell for low power application. IEEE Trans. Electron Dev. 66: 3834-3840.
)
