A design of improved nanoscale U-Shaped TFET by energy band modification for high performance digital and analog/RF applications

Document Type : Reasearch Paper

Authors

• Melisa Ebrahimnia ¹
• Seyed Ali Sedigh Ziabari ¹
• Azadeh Kiani-Sarkaleh ²

¹ Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.

² Department of Electrical Engineering, Energy and Building Research Center, Rasht Branch, Islamic Azad University, Rasht, Iran.

10.22034/ijnd.2021.681127

Abstract

In this study, a new nanoscale U-shaped tunnel field-effect transistor (US TFET) structure is proposed. In order to start the design process, the drain region of the conventional US TFET is divided into two distinct parts with N⁺ and N^- doping which is named the drain doping engineering (DDE). It is considered that the tunneling barrier at the channel-drain junction is increased and consequently the ambipolar current is decreased considerably. To continue the design process, the dual work function (DW) in the DDE-US TFET has been used to ameliorate the DC characteristics and the cutoff frequency. Moreover, we have used the metal implant (MI) in the source-side oxide of DDE-DW-US TFET as a technique to improve the device for high-frequency and low-power applications. The 2-D TCAD simulation results not only indicate the superiority of the proposed structure (DDE-DW-MI-US TFET) compared to others in terms of the high-frequency performance, but also illustrate the improvement of the DC parameters. Finally, the proposed device has been investigated by increasing the length of implanted metal in the source-side oxide. It is found that selecting the appropriate length contributes significantly to improve high-frequency performance.

Keywords

• Ambipolar Current
• Drain Doping Engineering
• Dual Work Function
• Metal Implant
• Nanoscale U-Shaped Tunnel Field-Effect Transistor (US TFET)

20.1001.1.20088868.2021.12.3.8.7

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References

[1] Kilchytska V., Neve A., Vancaillie L., Levacq D., Adriaensen S., Van Meer H., De Meyer K., Raynaud C., Dehan M., Raskin JP., (2003), Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Transact. Elect. Dev. 50: 577-588. 

[2] Abou-Allam E., Manku T., Ting M., Obrecht M. S., (2000), Impact  of technology scaling on CMOS RF devices and circuits. Proc. IEEE Custom Integr.Circuits Conf. 361-364.

[3] Strangio S., Palestri P., Lanuzza. M., Esseni. D., Crupi F., and Selmi L., (2017), Benchmarks of a III–V TFET technology  platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits. Solid State Elect. 128: 37-42.

[4] Ionescu A. M., Riel H., (2011), Tunnel field effect transistors as energy efficient electronic switches. Nature. 479: 329-337. 

[5] Bangsaruntip S., Cohen G. M., Majumdar A., Sleight J. W., (2010), Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Elect. Dev. Lett. 31: 903-905.

[6] Khorramrouz F., Sedigh Ziabari S. A., Heydari A., (2018), Analysis and study of geometrical variability on the performance of junctionless tunneling field efect transistors: Advantage o deiciency? Int. J. Nano Dimens. 9: 260-272. 

[7] Roy K., Mukhopadhyay S., Mahmoodi-Meimand H., (2003), Leakage current  mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE. 91: 305-327.

[8] Ionescu A. M., (2008), New functionality and ultra low power: Key opportunities for post-CMOS era. in Proc. Int. Symp. VLSI Technol. Syst., Appl. 72-73.

[9] Choi W. Y., Park B.-G., Lee J. D., Liu T.-J. K., (2007), Tunneling field-effect transistors (TFETs) with subthreshold swing (ss) less than 60 mV/Dec. IEEE Elect. Dev. Lett. 28: 743-745.

[10] Meshkin R., Sedigh Ziabari S. A., Rezaee Jordehi A., (2019), A novel analytical approach to optimize the work functions of dual-material double-gate Tunneling-FETs. Superlatt. Microstruct. 126: 63-71.          

[11] kazazis D., Jannaty P., Zaslavsky A., Le Royer C., Tabone C., Clavelier L., Cristoloveanu S., (2009), Tunneling field-effect transistor with epitaxial junction in thin germanium-on- insulator.  Appl. Phys. Lett. 94: 263508-263510.

[12] Uddin Shaikh M. R., Loan S. A., (2019), Drain-engineered TFET with fully suppressed ambipolarity for high-frequency application. IEEE Transact. Elect. Dev. 66: 1628-1634.

[13] Krishnamohan T., Kim D., Nguyen C. D., Jungemann C, Nishi Y., Saraswat K. C., (2006), High-mobility low band-to-band-tunneling strained-germanium double-gate heterostructure FETs: Simulations. IEEE Transact. Elect. Dev. 53: 1000 -1009.

[14] Lu H., Seabaugh A., (2014), Tunnel  field-effect  transistors: State-of-the-art. IEEE J. Elect. Dev. Soc. 2: 44-49.

[15] Seabaugh A. C., Zhang Q., (2010), Low-voltage tunnel  transistors for  beyond CMOS logic. Proc. IEEE. 98: 2095-2110.

[16] Aghandeh H., Sedigh Ziabari S. A., (2017), Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement. Superlatt. Microstruct. 111: 103-114.

[17] Verhulst S. A., Vandenberghe W. G., Maex K., Groeseneken G., (2007), Tunnel field-effect transistor without gate-drain overlap. Appl. Phys. Lett. 91: 053102-053104.                                                                                         

[18] Raad B. R., Sharma D., Nigam K., Kondekar P., (2016), Physics-based simulation study of  high-performance gallium arsenide phosphideindium gallium arsenide tunnel field-effect transistor. IET Micro. Nano Lett. 11: 366-368.

[19] Gupta S. K., Kulkarni J. P., Datta S., Roy K., (2012), Heterojunction intra-band tunnel FETs for low-voltage SRAMs. IEEE Transact. Elect. Dev. 59: 3533-3542.

[20] Raad B. R., Nigam K., Sharma D., Kondekar P. N., (2016), Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement. Superlatt. Microstruct. 94: 138-146.

[21] Tirkey S., Sharma D., Yadav D. S., Yadav S., (2017), Analysis of a novel metal implant junctionless tunnel FET for better DC and analog/RF electrostatic parameters. IEEE Transact. Elect. Dev. 64: 3943-3950.

[22] Choi W. Y., Lee W., (2010), Hetero-gate-dielectric tunneling field-effect transistors. IEEE Transact. Elect. Dev. 57: 2317-2319.

[23] Abdi D. B., Kumar M. J., (2014), Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J. Elect. Dev. Soc. 2: 187-190.

[24] Gupta S., Nigam K., Pandey S., Sharma D., Kondekar P. N., (2017),  Performance improvement of heterojunction double gate drain overlapped TFET using Gaussian doping, in Proc. 5th Berkeley Symp. Energy Efficient Elect. Syst. Steep Transistors Workshop (E3S),Berkeley, CA, USA. 1-3.

[25] Sahay S., Kumar M. J., (2015), Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX. IEEE Transact. Elect. Dev. 62: 3882-3886.

[26] Hraziia., Vladimirescu A., Amara A., Anghel C., (2012), An analysis on the ambipolar current in Si double-gate tunnel  FETs. Solid-State Elect. 70: 67-72.

[27] Vijayvargiya V., Vishvakarma S. K., (2014), Effect of  drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Transact. Nanotechnol. 13: 974-981.

[28] Raad B. R., Sharma D., Kondekar P., Nigam K., Yadav D. S., (2016), Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: A proposal, design, and investigation. IEEE Transact. Elect. Dev. 63: 3950-3957.

[29] Kim S. W., Kim J. H., King Liu T.-J., Cho i W. Y., Park B.-G., (2016), Demonstration of L-shaped tunnel field-effect transistors. IEEE Transact. Elect. Dev. 63: 1774-1778.  

[30] Wang W., Wang P.-F., Zhang C.-M., Lin X.,  Liu X.-Y.,  Sun Q.  Q.,  Zhou P.,  Zhang D. W., (2014), Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Transact. Elect. Dev. 61: 193-197.

[31] Chen S., Wang S., Liu H., Li W., Wang Q., Wang X., (2017), Symmetric U-shaped gate tunnel field-effect transistor. IEEE Transact. Elect. Dev. 64: 1343- 1349.

[32] Shaker A., El Sabbagh M., El-Banna M. M., (2017), Influence of drain doping engineering on the ambipolar conduction and high-frequency performance of TFETs. IEEE Transact. Elect. Dev. 64: 3541-3547.

[33] Chandan B. V., Nigam K., Sharma D., Tikival V., (2019), A novel methodology to suppress ambipolarity and improve the electronic characteristics of polarity-based electrically doped tunnel FET. Appl. Phys. A. 125: 81-87.

[34] Chandan B. V., Gautami M., Nigam K., Sharma D., Tikkiwal V. A.,Yadav S., Kumar S., (2018), Impact of a metal strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance. J. Comput. Elect. 18: 76-82.

[35] Boucart K., Ionescu A. M., (2007), Double-gate tunnel FET with high-κ gate dielectric. IEEE Transact. Elect. Dev. 54: 1725-1733.

[36] Solomon P. M., Jopling J., Frank D. J., D’Emic C., Dokumaci O., Ronsheim P., Haensch W. E., (2004), Universal  tunneling behavior  in technologically relevant  p/n junction diodes. J. Appl. Phys. 95: 5800-5812.

[37] Jamison P. C., Tsunoda T., Vo T. A., Li J., Jagannathan H., Shinde S. R., Paruchuri V. K., Gall D., (2015), SiO₂  free HfO₂ gate dielectrics by physical vapor deposition. IEEE Transact. Elect. Dev. 62: 2878–2882.

[38] Bagga N., Chauhan N., Banchhor S., Gupta D., Dasgupta S., (2019), Demonstration of a novel tunnel FET with channel sandwiched by drain. Semicond. Sci. Technol. 35: 015008.

[39] Lin R., Lu Q., Ranade P., King T. J., Hu C., (2002), An adjustable work function technology using Mo gate for CMOS devices. IEEE Elect. Dev. Lett. 23: 49-51.

[40] Johnson R. W., Hultqvist A., Bent S. F., (2015), A brief review of atomic layer deposition: From fundamentals to applications. Mater. Today. 17: 236-246.   

[41]  Tirkey S., Sharma D., Raad B. R., (2017), Introduction of a metal strip in oxide region of junctionless tunnel ield-efect transistor to improve DC and RF performance. J. Comput. Elect. 16: 714–720.

[42] Trndahl T., Ottosson M., Carlsson J.-O., (2004), Growth of copper metal  by atomic layer deposition using copper(I) chloride, water and hydrogen as precursors. Thin Solid Films. 458: 129-136.

[43] Sahoo S., Dash S., Routray S. R., Mishra G. P., (2020), Impact of drain doping engineering on ambipolar and high-frequency performance of ZHP line-TFET. Semicond. Sci. Technol. 35: 065003.

[44]  Rawat G., Talukdar J., Mummaneni K., (2019), A novel extended source TFET with δp⁺ - SiGe layer. Silicon. 12: 2273–2281.

[45] Paras N., Chauhan S. S., (2019), Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications. Microelect. Eng. 216: 111043-111050.   

[46] Chandan B. V., Dasari S, Yadav S., Sharma D., (2018), Approach to suppress ambipolarity and improve RF and linearity performances on ED-tunnel FET. IET Micro. Nano Lett. 13: 684-689.

[47] Bashir F., Loan S. A., Rafat M., Alamoud A. R. M., Abbasi S. A., (2015), A high-performance source engineered charge plasma-based Schottky MOSFET on SOI. IEEE Transact. Elect Dev. 62: 3357-3364.

[48] Meshkin R., Sedigh Ziabari S. A., Rezaee Jordehi A., (2020), Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: A 2D numerical simulation study. Semicond. Sci. Technol. 35: 065006.

[49] Ahish S., Sharma D., Kumar Y. B. N., Vasantha M. H., (2016), Performance  enhancement   of  novel  InAs/Si  hetero double-gate  tunnel  FET using Gaussian doping.  IEEE Transact.  Elect. Dev. 63: 288-295.

[50] Molaei Imenabadi R., Saremi M., Vandenberghe W. G., (2017), A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance. IEEE Transact. Elect.  Dev. 64: 4752-4758.